Xilinx Spartan-3A DSP Fpgas Xc3SD3400A-4fgg676c, Xc3SD3400A-4csg484I, Xc3SD1800A-4fgg676I, Xc3SD1800A-4fgg676c, Xc3SD1800A-4csg484I, Xc3SD1800A-4csg484c

XC3SD3400A-4FGG676C Description
The Spartan-3A DSP family expands on the success of the Spartan-3A FPGA family by introducing XtremeDSPTM DSP48A slices and increasing RAM per logic. New features increase system performance while lowering configuration costs. These Spartan-3A DSP FPGA improvements give more capability and bandwidth per dollar than ever before, setting a new benchmark for the programmable logic and DSP processing market. They work in conjunction with the industry-proven 90 nm process technology.
The Spartan-3A FPGA family is expanded and improved by the Spartan-3A DSP FPGAs. The XC3SD1800A and XC3SD3400A devices contain extra block RAM and XtremeDSP DSP48A slices and are designed for DSP applications. Based on the DSP48 blocks found in the Virtex®-4 devices, the XtremeDSP DSP48A slices replace the 18x18 multipliers present in Spartan-3A devices. An output register has also been added to the block RAMs to speed up performance. The Spartan-3A DSP devices' block RAM and DSP48A slices both operate at 250 MHz in the least expensive, standard-speed -4 grade.

XC3SD3400A-4FGG676C Features
 Very low cost, high-performance DSP solution for high-volume, cost-conscious applications
• 250 MHz XtremeDSP DSP48A Slices
• Dedicated 18-bit by 18-bit multiplier
• Available pipeline stages for enhanced performance of at least 250 MHz in the standard -4 speed grade
• 48-bit accumulator for multiply-accumulate (MAC) operation
• Integrated adder for complex multiply or multiply-add operation
• Integrated 18-bit pre-adder
• Optional cascaded Multiply or MAC
• Hierarchical SelectRAM memory architecture
• Up to 2268 Kbits of fast block RAM with byte write enables for processor applications
• Up to 373 Kbits of efficient distributed RAM
• Registered outputs on the block RAM with operation of at least 280 MHz in the standard -4 speed grade
• Dual-range VCCAUX supply simplifies 3.3V-only design
• Suspend, Hibernate modes reduce system power
• Low-power option reduces quiescent current
• Multi-voltage, multi-standard SelectIO interface pins
• Up to 519 I/O pins or 227 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• Selectable output drive, up to 24 mA per pin
• QUIETIO standard reduces I/O switching noise
• Full 3.3V ± 10% compatibility and hot swap compliance
• 622+ Mb/s data transfer rate per differential I/O
• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors

XC3SD3400A-4FGG676C Applications
Communications equipment
Industrial control systems
Military and aerospace systems
Medical equipment
Automotive systems
Consumer electronics